Exploiting Port Contention: A Side-Channel Timing Attack on Simultaneous Multi-threading (SMT) Processors

CVE-2018-5407 · MEDIUM Severity

CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:U/C:H/I:N/A:N

Simultaneous Multi-threading (SMT) in processors can enable local users to exploit software vulnerable to timing attacks via a side-channel timing attack on 'port contention'.

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